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PlanAhead Software 13.1
RTL Design Additions and Modifications
Text Editor Options
PlanAhead release 13 allows for customization of fonts for comments, and keywords,
supports integration of third-party text editors, and allows for easier use of Xilinx
Language Templates. See PlanAhead User Guide (UG632), Chapter 5, RTL Design.
IP Catalog
The PlanAhead release 13 enhancements in the IP Catalog are:
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The CORE Generator? software IP catalog now supports migration of older
superseded cores to the currently supported version.
PlanAhead now supports canceling IP generation tasks that block other operations in
the GUI.
Source File Exploration
PlanAhead can determine the top module in an RTL design automatically, or give you the
ability to define it manually.
You can reorder source files, either automatically or manually, for compilation and
synthesis, and automatically or manually enable or disable RTL source files as required by
the top-level module.
Power Estimation Enhancements
PlanAhead release 13 has Power Estimation available on Virtex-5, Virtex-6, and Spartan?-
6 device families.
Partitions Control
PlanAhead release 13 provides control of partitions at the RTL level in synthesis with XST.
Additional ChipScope Features
The PlanAhead software release 13 added the ability within the ChipScope? Pro Debug
Analyzer to tag RTL nets using a new HDL Debug Probe feature that supports the
following HDL debug flows:
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PlanAhead and Xilinx Synthesis Technology (XST).
PlanAhead and Synplify and Synplify Pro from Synopsys, Inc.
PlanAhead and Precision RTL Synthesis from Mentor Graphics, Inc.
See Chapter 12, Programming and Debugging the Design, in the PlanAhead User Guide
(UG632).
Pin Planning Changes
The following subsections describe the PlanAhead 13 changes to the pin planning features.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
www.xilinx.com
35
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